| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 10.00 | 10.00 |
| Total | Covered | Percent | |
|---|---|---|---|
| Totals | 10 | 1 | 10.00 |
| Total Bits | 20 | 2 | 10.00 |
| Total Bits 0->1 | 10 | 1 | 10.00 |
| Total Bits 1->0 | 10 | 1 | 10.00 |
| Ports | 10 | 1 | 10.00 |
| Port Bits | 20 | 2 | 10.00 |
| Port Bits 0->1 | 10 | 1 | 10.00 |
| Port Bits 1->0 | 10 | 1 | 10.00 |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 | Direction |
| VDD | No | No | No | INPUT |
| VSS | No | No | No | INPUT |
| Q | No | No | No | OUTPUT |
| SO | No | No | No | OUTPUT |
| CK | No | No | No | INPUT |
| D | Yes | Yes | Yes | INPUT |
| SD | No | No | No | INPUT |
| SE | No | No | No | INPUT |
| RN | No | No | No | INPUT |
| notifier | No | No | No | INPUT |
| Name | Toggle | Toggle 1->0 | Toggle 0->1 |
| CE | Unreachable | Unreachable | Unreachable |
| SN | Unreachable | Unreachable | Unreachable |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |